Multiple Word Length based low power digital base band receiver

In recent years power consumption in CMOS VLSI circuits has become a major design constraint. This is in particular important for mobile wireless communication systems, due to the limited life time of the batteries to power wireless communication equipment. The circuit designers came with suitable low power strategies to achieve low power design. These circuit level techniques are readily available in the form of standard cells to the Register Transfer Level (RTL) designer. Currently designers are exploring the algorithm level and architecture level techniques towards arriving at low power communication Integrated Circuits (ICs). The Word Length Optimization (WLO) is an algorithmic approach with promising power saving levels, suitable for communication applications. The work presented here demonstrates power optimized RTL design for wireless base band receiver using Quadrature Phase Shift Keying (QPSK) modulation scheme. The novel method of arriving at suitable word lengths based on system level parameters at each signal stage is demonstrated. The Symbol Error Rates (SER) for given energy per symbol are analyzed. The Xilinx Zynq-7 Family FPGA is used for area, power and performance analysis. The peak power optimization of 40% is reported for Es/No = 8 dB, in comparison to the normal design.